Operating Conditions
| Enable Criteria | Ignition ON |
| Failure Criteria | When UVW-phase current sampling the acquisition value is greater than 4.97V, or the acquisition value is less than 0.03V CPLD base on speed fault is considered to occur when CPLD sends back PWM life signal fault; CPLD external clock fault signal sent by CPLD to lvmcu through IO port; CPLD three-phase over current (830A) Parity failure of CPLD back signal; Fault of SPI communication sent back by CPLD; CPLD bus overvoltage (550V). CPLD Fault is considered to occur when Cpld sends a Cpld external clock fault signal to Lvmcu via SPI; CPLD sends back Nen signal failure; Short circuit fault of Upper bridge driver chip on CPLD send; Short circuit fault of down bridge driver chip on CPLD send; Fault of sztkt signal sent back by CPLD; Power supply under voltage (20 V) fault of Upper bridge driver chip on CPLD send back; Power supply under voltage (16 V) fault of down bridge driver chip on CPLD send back faults happen. |
| Failure/Mature Time | 500 ms |
| Pass Criteria | When UVW-phase current sampling the acquisition value is less than 4.97V, and the acquisition value is more than 0.03V When CPLD sends back PWM life, signal no fault; CPLD extern clock fault signal no sent by CPLD to lvmcu through IO port; CPLD three-phase no overcurrent fault; No Parity failure of CPLD back signal; No Fault of SPI communication sent back by CPLD; CPLD bus overvoltage faults not happen. When Cpld sends a Cpld external clock fault signal to Lvmcu via SPI; CPLD no sends back Nen signal failure; No Short circuit fault of Upper bridge driver chip on CPLD send; No Short circuit fault of down bridge driver chip on CPLD send; No Fault of sztkt signal sent back by CPLD; Power supply no under voltage fault of Upper bridge driver chip on CPLD send back; Power supply no under voltage fault of down bridge driver chip on CPLD send back faults not happen |
| Pass/De-mature Time | 500 ms |
| Failure Aging | 40 Ignition cycles. |